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This is where I will update my daily progress and activities.

Week 5 Learning Log (June 16–20, 2025) # 1. Objectives # Library Documentation

Week 4 Learning Log (June 9–13, 2025) # 1. Objectives # Literature Review & Blogging

Week 3 Learning Log (June 2–6, 2025) # 1. Objectives # ALU Implementation & Testing Design a simple 4-bit ALU using Vivado IP Integrator arithmetic blocks (alu_bd.

This is the first chapter of the book. I divided my thoughts and summary into four sections:

As part of my internship, I decided to read “Computer Organization and Design RISC-V edition” by David A.

Week 2 Learning Log (May 26–30, 2025) # 1. Objectives # HDL Implementation & Simulation Implement and simulate the following combinational primitives: 4-bit Subtractor (subtractor4.

Here, I will be updating what I learned about computer organization and architecture.

Week 1 Learning Log (May 19–23, 2025) # 1. Objectives # FPGA Architecture & Tools Understand FPGA internal architecture: CLBs (LUTs, muxes, flip-flops), on-chip SRAM/Block RAM Install and configure Vivado/Vitis 2022.

Motivation for the Internship: # I am passionate about forging a career in research and innovation within computer engineering. This internship offers a unique opportunity to translate my theoretical knowledge into hands-on expertise by designing and building a processor from the ground up.

System Verilog is a hardware desciption language that builds on Verilog.

SRAMs are static memory. They are implemented using 6 transistors usually and because of that more expensive.

Definition # Look up table is a memory. Instead of recomputing a circuit or a logic function every time, we compute and store in LUTs.

This is where I will be adding entries on theories and concepts I learned along the way and would like to look back and reference.

Nets model physical connections between drivers. When you have multiple drivers

The architecture of FPGAs rely heavily on Configuration Logic Blocks (CLBs).

At the heart of an SRAM cell lies a bistable flip-flop, which is a circuit capable of holding one of two stable states: logic ‘0’ or logic ‘1’.

Benchmarking the Intel Core I7 # SPEC CPU Benchmark # If you had 2 computers, how would you know one of them performed better than the other?

Performance # When you are choosing a computer, how should you choose?

Below Your Program # For computers to run complex applications, there needs to be some sort of translation.