Module Inventory

This document catalogs every leaf RTL block under modules/.
(For full repo layout, refer to 01-overview).

Folder Sub-tree

RVSvKit/
└── modules/
    ├── arithmetic/
    │   ├── half_adder/
    │   ├── adder/
    │   ├── multiplier/
    │   ├── divider/
    │   └── alu/
    ├── logic/
    │   ├── comparator/
    │   ├── bitwise_and/
    │   ├── bitwise_or/
    │   ├── bitwise_xor/
    │   └── mux/
    ├── register/
    │   ├── register/
    │   ├── pipeline_reg/
    │   └── reg_file/
    ├── control/
    │   ├── immediate_generator/
    │   ├── branch_unit/
    │   ├── control_fsm/
    │   ├── instruction_decoder/
    │   ├── csr_unit/
    │   └── trap_handler/
    ├── memory/
    │   ├── load_store_unit/
    │   ├── fifo/
    │   └── cache_wrap/
    ├── pipeline/
    │   ├── decoupled_reg/
    │   ├── hazard_unit/
    │   ├── forwarding_unit/
    │   └── wb_mux/
    ├── peripheral/
    │   └── clint/
    └── debug/
        └── dtm/

1. Initial Modules

arithmetic/

half_adder — 1-bit sum & carry
adder — N-bit addition/subtraction with carry in/out
multiplier — iterative or Booth-based multiplier
divider — restoring/non-restoring divider
alu — composite ALU (add/sub, bitwise ops, shifts, comparisons)

logic/

comparator — equality, inequality, signed/unsigned comparisons
bitwise_and — bitwise AND operation
bitwise_or — bitwise OR operation
bitwise_xor — bitwise XOR operation
mux — 2-to-1 / N-to-1 multiplexers

register/

register — parameterized flip-flop with synchronous reset
pipeline_reg — ready-valid handshake pipeline register
reg_file — 32×XLEN-bit register file (2 read, 1 write)

control/

immediate_generator — sign-extends I/S/B/U/J immediates
branch_unit — branch condition evaluation & target calculation
control_fsm — pipeline stall/flush FSM
instruction_decoder — opcode/funct3/funct7 bit-field extraction
csr_unit — manages mstatus, mepc, mtvec, and CSR accesses
trap_handler — exception & interrupt flow control

memory/

load_store_unit — aligned/misaligned loads & stores
fifo — synchronous FIFO with status flags
cache_wrap — write-through cache wrapper

pipeline/

decoupled_reg — back-pressure-aware pipeline register
hazard_unit — RAW/WAR/WAW hazard detection
forwarding_unit — data bypass network for EX stage
wb_mux — selects ALU result, load data, or CSR output

peripheral/

clint — core-local interrupt controller (mtime, msoft)

debug/

dtm — JTAG/SWD Debug Transport Module

2. Future Modules Future Modules

Multiplier/divider variants — pipelined, SRT, non-restoring algorithms
Cache enhancements — write-back, set-associative, MESI protocol
MMU stubs — simple page tables & TLB interfaces
DRAM controller — AXI-compliant DDR3/DDR4 interface
Vector unit — RVV-style SIMD lanes

Overview Coding Conventions