Skip to main content
  1. Posts/
  2. System Verilog/

Practical/Implementation knowledge

There are some mistakes I made when I was developing the library and I would like to update them here for reference later.

Debugging a Half-Adder Testbench: A Journey in Four Lessons
365 words·2 mins
When I set out expecting a quick smoke test for my pure combinational half-adder in SystemVerilog, I expected it to be trivial.