Language Concepts

Both functions and tasks are subroutines that are reusable RTL or testbench codes.

Every module or interface exposes a list of ports - points of connection where signal, handshakes or buses flow in and out.

Nets model physical connections between drivers. When you have multiple drivers

SystemVerilog introduces logic as a 4-state data type that can be assigned in initial, always, or always_comb blocks.