System Verilog
System Verilog is a hardware desciption language that builds on Verilog. It adds high-level constructs for design, simulation, and formal verification, making it a popular choice for modern chip design workflows.
Practical/Implementation knowledge
23 words·1 min
There are some mistakes I made when I was developing the library and I would like to update them here for reference later.
Language Concepts
6 words·1 min
This folder contains system verilog concepts.