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07-contributing-and-versioning

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Connie
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Connie
Optimistic undergrad
Table of Contents

Contributing & Versioning
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This document outlines how to contribute to RVSvKit, our branching and release policies, and our roadmap for future enhancements. It’s designed to align with the Overview and Module Inventory docs.

1. Contributing Guidelines
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  • Contributions Status

    • At present, RVSvKit is not accepting external PRs until we formalize the module API and CI stability.

    • We plan to open contributions when the core API (under modules/, common/, protocols/) reaches version 1.0.0.

  • Future Process

    • We will provide a CONTRIBUTING.md template with:

      • Issue template (bug report, feature request)

      • PR template (description, test instructions, impact analysis)

    • All contributions will require:

      1. Pass all CI pipelines (verilator.yml, vivado_docker.yml)

      2. Adhere to 03-coding-conventions.md style rules

      3. Update ci/benchmark CSV if resource usage changes

      4. Include or update tests in the appropriate tb/ directory

2. Branching & Release Policy
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  • Branching Model

    • main branch holds the latest stable release.

    • Feature branches prefixed with feature/ for new API or core modules.

    • Hotfix branches prefixed with hotfix/ for critical bug fixes against releases.

  • Versioning

    • We follow Semantic Versioning: MAJOR.MINOR.PATCH

      • MAJOR: incompatible API or backward-breaking changes

      • MINOR: backward-compatible feature additions

      • PATCH: backward-compatible bug fixes

  • Release Checklist

    1. All CI pipelines pass

    2. Changelog entry in docs/CHANGELOG.md

    3. Tag release in Git: vX.Y.Z

    4. Update version in common/pkg/common_pkg.sv header comment

    5. Publish GitHub release with release notes

3. Roadmap & Future Improvements
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We strive for incremental progress with clear ETAs (quarters refer to calendar year 2025):

FeatureStatusETA
CSR file & trap handlerIn designQ3 2025
Multiplier/divider variantsPlannedQ4 2025
Cache enhancements (write-back)PlannedQ1 2026
MMU stubs & TLB interfacesResearchQ2 2026
DRAM controller (DDR3/DDR4)FutureQ3 2026
Vector unit (RVV lanes)FutureQ4 2026

4. Open Ideas & Feedback
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  • We welcome internal team discussions via GitHub Discussions or project boards before opening to the public.

  • If you have suggestions—module ideas, protocol enhancements, automation tips—please document them as GitHub Issues under the appropriate label: enhancement, performance, or docs.

Refer to 01-overview for full repo layout, 02-module-inventory for module catalog, and 03-coding-conventions for pipeline details.