RVSvKit - RISC V System Verilog Kit

Overview # Welcome to RVSvKit, a lightweight, parameterized SystemVerilog library for building RISC-V–style pipelines and peripherals.

Module Inventory # This document catalogs every leaf RTL block under modules/.

Coding Conventions # This guide defines the SystemVerilog style and naming rules for RVSvKit, ensuring consistency with the Overview and Module Inventory.

Packages & Interfaces # This document outlines the shared packages and bus-interface abstractions for RVSvKit, consistent with the Overview and Module Inventory.

CI & Testing # This document defines the continuous-integration pipelines, smoke synthesis, functional regression, benchmarking, and gating thresholds for RVSvKit, consistent with the Overview and Module Inventory.

Automation & Optimization # This document describes the scaffolding tools, CI/CD automation, parameter sweeps, RTL optimization guidelines, and static-analysis reporting for RVSvKit, consistent with Overview and Module Inventory.

Contributing & Versioning # This document outlines how to contribute to RVSvKit, our branching and release policies, and our roadmap for future enhancements.