Learning Logs

Week 5 Learning Log (June 16–20, 2025) # 1. Objectives # Library Documentation

Week 4 Learning Log (June 9–13, 2025) # 1. Objectives # Literature Review & Blogging

Week 3 Learning Log (June 2–6, 2025) # 1. Objectives # ALU Implementation & Testing Design a simple 4-bit ALU using Vivado IP Integrator arithmetic blocks (alu_bd.

Week 2 Learning Log (May 26–30, 2025) # 1. Objectives # HDL Implementation & Simulation Implement and simulate the following combinational primitives: 4-bit Subtractor (subtractor4.

Week 1 Learning Log (May 19–23, 2025) # 1. Objectives # FPGA Architecture & Tools Understand FPGA internal architecture: CLBs (LUTs, muxes, flip-flops), on-chip SRAM/Block RAM Install and configure Vivado/Vitis 2022.

mon, 23 june calas meeting changed icarus simulation to use verilator instead, which included: writing sim_main.