Posts

This is where I will update my daily progress and activities.

Here, I will be updating what I learned about computer organization and architecture.

Motivation for the Internship: # I am passionate about forging a career in research and innovation within computer engineering. This internship offers a unique opportunity to translate my theoretical knowledge into hands-on expertise by designing and building a processor from the ground up.

System Verilog is a hardware desciption language that builds on Verilog.

I am developing my own library / development kit for the ease of use when I experiment more with RISC V architecture.

This is where I will be adding entries on theories and concepts I learned along the way and would like to look back and reference.