Data Type: Nets
Nets model physical connections between drivers. All net types are inherently four-state - each bit can be 0, 1, X (unknown) or Z (high-impedance). This is due to several reasons.
Nets have to have more than 2 states (binary values) because they allow multiple drivers. They must allow X and Z states to model un-driven or partially-driven connections. When there are multiple sources (like bus signals or tri-state buffers), there might be a conflict. When there is a conflict the net will have X value and Z if there is no drivers.
Floating (Z)
The z state specifically refers to a floating or un-driven condition—the net is not being actively driven by any source.
When there are multiple drivers:
- If one driver puts
zand another puts1, the result is1. - If one driver puts
zand another putsz, the result isz. - If one driver puts
1, another puts0, result isx(conflict).
Contention (X)
Since multiple drivers can “pushes” a value to the same port, there would be some conflict. In that case, simulation resolves it to X to flag the conflict.
module A(output wire a); assign a = 1; endmodule
module B(output wire b); assign b = 0; endmodule
wire foo;
A u1(.a(foo));
B u2(.b(foo));
// foo sees 1 from A and 0 from B → foo becomes X (conflict)
Contention Resolution
Whenever there is a conflict, simulation uses a table shown below to resolve the conflict:
| Driver A \ Driver B | 0 | 1 | X | Z |
|---|---|---|---|---|
| 0 | 0 | X | X | 0 |
| 1 | X | 1 | X | 1 |
| X | X | X | X | X |
Net Types
- Basic Nets Wires require one driver or resolves them using wired logic. It simply represents a physical connection.
wire(4-state): the most common netwire [N-1:0] busis simply an N-bit vector of wires. It is N individual 1-bit nets all bundled under one name. It tells the compiler “I want N separate wires, numbered 0 through N-1". On an FPGA or ASIC, each bit of that vector becomes its own metal interconnect (or FPGA routing wire). When you hook a 32-bit bus between two modules, the placer & router will physically lay out 32 parallel tracks.
- Pulled Nets: It is an alias for wire, but used when we expect there to be multiple drivers. It has pull up, which means a default state when there are no drivers.
tri0/tri1: when undriven, defaults to 0 or 1.trireg: - likewire, but with an implicit pull-down resistor.
- Wired-AND / Wired-OR
They are resolved net types. Instead of returning
xon multiple conflicting drivers,wandandworresolve the multiple drivers using logic rules:
wand: Open-drain: any driver pulling low causes low output. All must be high (or unconnected) for output to be high.wor: Open-source: any driver pulling high causes high output. All must be low (or unconnected) for output to be low.
- Supply Nets Supply nets have constant voltage tied to it. It is either logical high or low. Think of them as your power supply/ground for your circuit.
supply1models a net tied directly to Vcc (logic high).supply0models a net tied directly to GND (logic low).
Summary Table
| Net Group | Net Names | Default | Resolves? | Use Case |
|---|---|---|---|---|
| Unresolved nets | wire, tri | 'z | No (→ ‘X’ on conflict) | general signals / tri-state bus |
| Pulled nets | tri0, tri1 | 0 / 1 | No | open-collector/drain defaults |
| Wired-logic nets | wand/wor | 'z | Yes (AND / OR) | wired-AND/OR buses |
| Variants | wand0, wor1 | 0 / 1 | Yes (AND / OR) | same, with fixed default |
| 2-state net | uwire | 0 | No | efficient internal wiring |
| Power rails | supply0, supply1 | 0 / 1 | Constant | GND/VCC modeling |