Testing RTL modules

First, you can create your own testbench files, but moving on, for more extensive testing, you can use .tv which stands for test vector file. For this, you can make them yourself, or use repositories such as https://github.com/chipsalliance/riscv-vector-tests.

.tv files just contain binaries.

Next, you can test the signature dump using riscvOVPsim. riscvOVPsim creates a test file, which you can load to your memory, after you run the code, your core should create a signature dump. You can then compare and test them.