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      • Welcome!
        • Computer Organization
          • Computer Organization and Design RISC-V edition
            • Chapter 1 - Computer Abstractions and Technology
              • Part 1: Foundations & “Eight Great Ideas”
              • Part 2: Inside the Machine – Abstraction Layers & Technologies
              • Part 3: Performance, Power & the “Sea Change”
              • Part 4: Real-World Examples & Wrap-Up
            • Chapter 2
              • Part 1: Introduction to Computer Instructions
              • Part 2: Instruction Representation and Logic
              • Part 3-1: Procedures
              • Part 3-2: Memory & Addressing
          • Hardware Components
            • ALU Control
            • Control signals
            • Data Memory
            • Immediate Generator
            • Pipeline registers.
            • Program counter
            • Register File in RISC V
          • Instruction Behavior
            • Base Intructions
            • Immediate Formats in RISC V
            • Stage-by-Stage Datapath
          • Diagrams and Reference
            • Simple RISC V core diagram
            • Different type of core
        • Digital Logic Circuits
          • 555 Timers
          • Bi-stable Flip Flop
          • Configuration Logic Block
          • LUT
          • SRAM
        • Operating Systems
          • Parallelism, concurrency in OS and Hardware
          • Processes ERD
          • Runtime stack ERD
        • Practical Learnings
          • Datapath
          • Testing RTL modules
        • RISC V assembly
        • System Verilog
          • Language Concepts
            • Data Type: Nets
            • Ports
          • Practical/Implementation knowledge
            • Some Common Mistakes
            • Debugging a Half-Adder Testbench: A Journey in Four Lessons
      • About
      • Projects
        • RVSvKit - RISC V System Verilog Kit
          • Overview
          • Module Inventory
          • Coding Conventions
          • Packages and Interfaces
          • CI and Testing
          • Automation Optimization
          • Contributing and Versioning
      • Computer Organization
        • Computer Organization and Design RISC-V edition
          • Chapter 1 - Computer Abstractions and Technology
            • Part 1: Foundations & “Eight Great Ideas”
            • Part 2: Inside the Machine – Abstraction Layers & Technologies
            • Part 3: Performance, Power & the “Sea Change”
            • Part 4: Real-World Examples & Wrap-Up
          • Chapter 2
            • Part 1: Introduction to Computer Instructions
            • Part 2: Instruction Representation and Logic
            • Part 3-1: Procedures
            • Part 3-2: Memory & Addressing
        • Hardware Components
          • ALU Control
          • Control signals
          • Data Memory
          • Immediate Generator
          • Pipeline registers.
          • Program counter
          • Register File in RISC V
        • Instruction Behavior
          • Base Intructions
          • Immediate Formats in RISC V
          • Stage-by-Stage Datapath
        • Diagrams and Reference
          • Simple RISC V core diagram
          • Different type of core
      • Digital Logic Circuits
        • 555 Timers
        • Bi-stable Flip Flop
        • Configuration Logic Block
        • LUT
        • SRAM
      • Operating Systems
        • Parallelism, concurrency in OS and Hardware
        • Processes ERD
        • Runtime stack ERD
      • Practical Learnings
        • Datapath
        • Testing RTL modules
      • RISC V assembly
      • System Verilog
        • Language Concepts
          • Data Type: Nets
          • Ports
        • Practical/Implementation knowledge
          • Some Common Mistakes
          • Debugging a Half-Adder Testbench: A Journey in Four Lessons
      Edit this page on GitHub →
      Welcome!
      Computer Organization
      Computer Organization and Design RISC-V edition
      Chapter 2

      Chapter 2

      Blog 1: Intro to Instructions
      Foundational concepts of how computers process instructions and data.
      Blog 2: Representation & Logic
      How instructions are encoded and how computers make logical decisions.
      Blog 3: Procedures & Addressing
      Interaction between hardware and software, and addressing techniques.
      Blog 4: Parallelism & Execution
      Advanced execution concepts and a practical sort example.
      Blog 5: Arrays & Compilation
      Memory handling and compilation techniques in C and Java.
      Blog 6: ISAs & Final Thoughts
      Instruction sets, common pitfalls, and historical context.