ALU Control

ALU Control Overview

In the RV32I single-cycle core, the ALU Control module translates a 2-bit ALUOp signal from the Control Unit and the instruction’s funct3 and funct7[5] bits into a 4-bit ALUCtrl code that drives the ALU datapath.

Inputs and Output

ALUOp [1:0] — broad operation class from control.v
funct3 [2:0] — instruction-specific bits
funct7[5] — bit 5 of the funct7 field
ALUCtrl [3:0] — selects the exact ALU operation, matching the localparam definitions in alu.v

ALUCtrl Encoding Table

ALUOp	funct7[5]	funct3	ALUCtrl	Operation
`00`	—	—	`0000`	ADD (load/store/AUIPC)
`01`	—	—	`0001`	SUB (branch compare)
`10`	`0`	`000`	`0000`	ADD
`10`	`1`	`000`	`0001`	SUB
`10`	`0`	`001`	`0010`	SLL
`10`	`0`	`010`	`0011`	SLT
`10`	`0`	`011`	`0100`	SLTU
`10`	`0`	`100`	`0101`	XOR
`10`	`0`	`101`	`0110`	SRL
`10`	`1`	`101`	`0111`	SRA
`10`	`0`	`110`	`1000`	OR
`10`	`0`	`111`	`1001`	AND
`11`	—	—	`1010`	LUI (pass upper immediate)

Verilog Implementation

module alu_control(
  input  wire [1:0] ALUOp,
  input  wire [2:0] funct3,
  input  wire       funct7_5,
  output reg  [3:0] ALUCtrl
);

  always @(*) begin
    case (ALUOp)
      2'b00: ALUCtrl = ALU_ADD;
      2'b01: ALUCtrl = ALU_SUB;
      2'b11: ALUCtrl = ALU_ADD;  // LUI: pass immediate upper bits
      2'b10: begin
        case ({funct7_5, funct3})
          4'b0_000: ALUCtrl = ALU_ADD;
          4'b1_000: ALUCtrl = ALU_SUB;
          4'b0_001: ALUCtrl = ALU_SLL;
          4'b0_010: ALUCtrl = ALU_SLT;
          4'b0_011: ALUCtrl = ALU_SLTU;
          4'b0_100: ALUCtrl = ALU_XOR;
          4'b0_101: ALUCtrl = ALU_SRL;
          4'b1_101: ALUCtrl = ALU_SRA;
          4'b0_110: ALUCtrl = ALU_OR;
          4'b0_111: ALUCtrl = ALU_AND;
          default:  ALUCtrl = ALU_ADD;
        endcase
      end
    endcase
  end
endmodule

This implementation cleanly separates opcode-level decoding (in the Control Unit) from the ALU’s fine-grained operation selection.

Control signals