Connie

Week 5 Learning Log (June 16–20, 2025) # 1. Objectives # Library Documentation

Week 4 Learning Log (June 9–13, 2025) # 1. Objectives # Literature Review & Blogging

Week 3 Learning Log (June 2–6, 2025) # 1. Objectives # ALU Implementation & Testing Design a simple 4-bit ALU using Vivado IP Integrator arithmetic blocks (alu_bd.

As part of my internship, I decided to read “Computer Organization and Design RISC-V edition” by David A.

SRAMs are static memory. They are implemented using 6 transistors usually and because of that more expensive.

Definition # Look up table is a memory. Instead of recomputing a circuit or a logic function every time, we compute and store in LUTs.

The architecture of FPGAs rely heavily on Configuration Logic Blocks (CLBs).

Overview # Welcome to RVSvKit, a lightweight, parameterized SystemVerilog library for building RISC-V–style pipelines and peripherals.

Module Inventory # This document catalogs every leaf RTL block under modules/.

Coding Conventions # This guide defines the SystemVerilog style and naming rules for RVSvKit, ensuring consistency with the Overview and Module Inventory.

This folder contains system verilog concepts.

There are some mistakes I made when I was developing the library and I would like to update them here for reference later.